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Description: AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
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Size: 5120 |
Author: local_boy
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Description: Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc.
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Size: 17010 |
Author: sunhaichaook@163.com |
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Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。
SPI相关缩写
SS: Slave Select，选中从设备，片选。
CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性
CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位
SCK = SCLK = SCL = SPI的时钟（Serial Clock）
Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。
对于一个时钟周期内，有两个edge，分别称为：
Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候；
Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices.
SPI related abbreviations
SS: Slave Select, selected from the device, chip select.
CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity
CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase
SCK = SCLK = SCL = SPI clock (Serial, Clock)
Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge).
For a clock cycle, there are two edge, respectively:
Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1;
Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;)
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Size: 6144 |
Author: helimpopo
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
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Size: 523264 |
Author: 冰激凌很牛
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Description: sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
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Size: 12288 |
Author: 风雪来 |
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Description: JPEG_d IP Core Verilog crypted source
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Size: 15606784 |
Author: 发企鹅出去啊 |
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Description: 8051 Core Verilog RTL IP Code
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Size: 1597440 |
Author: richman |
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